SI-MOD32xx Block Diagram

SI-MOD32xx Circuit Reference

ADC Circuitry

The FPGA controls up to four (4) ADAS3022, 16 bit, 8 channel 1Mhz additive sampling ADC devices, for up to a maximum of 32 input channels with bipolar inputs that ranges between ±10V (20Vpp).

The only ancillary front end circuit includes a passive, single pole low pass RC filter with Fc = 482.3khz for each input.

The following ADAS3022 pins are tied to the FMC connector and are controlled by the carrier's FPGA with +2.5Vdc~+3.3Vdc compatibility:

DAC Circuitry

The FPGA controls up to two (2) LTC2666, 16 bit, 8 channel 250khz additive updating DAC devices, for up to a maximum of 16 output channels. Each DAC output channel is buffered with a voltage opamp.

The LTC2666 is configured by default to operate in bipolar mode with outputs that range ±10V (20Vpp) where the configuration pins MSP[2:0] = LO. However, please consult the factory to change the default operating mode to one of the various available unipolar or bipolar modes, or a mode where the ranges are set in software.

The following LTC2666 pins are tied to the FMC connector and are controlled by the carrier's FPGA with +2.5Vdc~+3.3Vdc compatibility:

DIO Circuitry

The FPGA controls four (4) 74FCT2652 8 bit transceivers, with two (2) devices making up each 16 bit bidirectional buffered port, for a maximum thirty two (32) lines, with +3.3Vdc~+5Vdc tolerance on the IO lines. When a port is configured as an input, it operates as a non-registered transceiver. Meanwhile as an output, it operates as a registered transceiver.

SI-MOD32xx Connector Reference

Analog IO Connections

Analog IO Connector: External 30 Pin Connector Pair

A pair of generic 30 pin, 0.050" pitch (1.27mm) connectors are used to interface the external analog I/O signals. Below is the connection diagram:

ADC & DAC Interconnections Between FMC Connector & FPGA

Below is a chart of the four (4) ADC and two (2) DAC interconnections between the FMC connector's LPC columns, and the Altera Cyclone 5GX FPGA device:

NOTES:

1. The analog inputs have a maximum range of ±10Vp (20Vpp), with gains of 1, 2, 4, & 10, and a maximum additive sampling rate of 1Msps per every group of 8SE/4DE channels.
2. The analog outputs have a maximum range of ±10Vp (20Vpp), with an update rate of up to 250Ksps per output channel.
3. Complete SI-MOD32xx specifications may be found here:
   https://sheldoninstruments.com/products/hardware/multifunction-io-boards/p=si-mod32xx/
   
   

SI-MOD32xx Digital IO Connections

Digital IO Port Connector: External 40 pin Connector

A generic 40 pin, 0.050" pitch (1.27mm) connector is used to interface the external digital I/O signals. Below is the connection diagram:

NOTES:

1. The buffered 32 DIO lines are +3.3Vdc signals that are optionally +5Vdc tolerant.
   

Digital IO Interconnections Between FMC Connector & FPGA

Below is a chart of the 32 bit Digital I/O Port interconnections between the FMC connector's extra HPC columns, and the Altera Cyclone 5GX FPGA device:

FMC Connector

When the FMC connector is configured with the 200 contact Low Pin Count (LPC) option with only columns C-D-G-H defined, all analog I/O circuits and signals are supported. On the other hand, when the FMC connector on the carrier is configured with the 400 contact High Pin Count (HPC) option with all columns defined, the additional dual 16 bit port, 32 bit digital IO signals are also supported. Below is the connection diagram:

NOTES:

1. The VADJ_A_C2M rail for powering the LA & HA busses connected to the FPGA's VIO lines is defaulted at +3.3Vdc, but supports ranges between +2.5Vdc to +3.3Vdc.
2. The VREF_A_M2C, VIO_B_M2C, VREF_B_M2C, and 3.3V_AUX not used.
   
   

Power Consumption